The invention described herein relates generally to semiconductor devices and processing. In particular, the invention relates to capping layers used on copper conducting structures in semiconductor devices and related fabrication methods. More particularly, the invention relates to methods and structures for creating self-aligned alloy capping layers on copper conducting structures.
The semiconductor industry has moved to using copper in various aspects of semiconductor devices due to certain advantages of copper over other metals. Copper has lower resistivity than, for example, aluminum. As a result, copper circuitry suffers less from resistance-capacitance (RC) delays. This makes copper systems faster. Further, copper has increased resistance to electromigration, thereby enabling smaller scaling of semiconductor devices. However, with increased use, certain problems particular to copper have become more prevalent. One such problem is that copper materials have high diffusivity through dielectric and silicon materials in which the copper is deposited. This is problematic because the presence of copper in these materials may xe2x80x9cpoisonxe2x80x9d the materials and lead to semiconductor device failure.
In conventional methodologies, a barrier material is typically deposited on the dielectric material between the copper layer and the dielectric (or silicon) material, thereby preventing the copper from diffusing into the dielectric or silicon material. Typically, tantalum (Ta) or titanium (Ti) based barrier materials (e.g., tantalum nitrides (TaN), tantalum silicon nitrides (TaSiN), or titanium nitrides (TiN)) are used as barrier layers for copper. Additionally, copper layers are covered in a capping layer that also serves as a barrier to copper diffusivity. Thus, copper layers are completely encased in barrier materials. Conventional capping layers are formed of barrier materials, for example, silicon nitride (such as Si3N4) materials. However, such materials also have limitations. One disadvantage of Si3N4 materials is the capacitance problems such materials create. Also, such materials can have porous boundaries which create unwanted copper diffusion paths. Additionally, the thickness of existing barrier layers create some difficulties as feature size decreases. This is especially true as feature sizes decrease below 0.18 (xcexc) micron.
A conventional prior art process for creating a copper conducting structure is described hereinbelow with respect to FIGS. 1-5. In FIG. 1, a typical semiconductor wafer 100 is placed in a process chamber 101 and various layers of material and circuit structures are formed thereon.
FIG. 2 is a cross-section view of a portion of semiconductor substrate. The depicted substrate includes a dielectric layer 201 having an opening therein 202. In the depicted illustration the opening 202 defines a via structure having a conducting plug 203 at its bottom. The conducting plug 203 connects to an underlying conducting layer 204. The conducting layer 204 can be electrically connected to an active device or underlying metal or interconnect layers formed on the wafer (or substrate). Such openings can define a wide range of features or devices, including but not limited to vias, trenches, or inter-level interconnect structures. Such structures can be fabricated using conventional techniques known to one skilled in the art. The dielectric layer 201 can be formed of many dielectric materials including silicon dioxide; however, combinations of silicon dioxide and other doped dielectrics (e.g. BPSG, PSG) are also commonly used. In addition, low-K dielectric materials can be used. This opening in the dielectric layer 201 can be filled to with conducting materials to form conducting structures.
FIG. 3 shows the topmost portion of FIG. 2. An insulating layer 201 is formed over the substrate surface, including plug 203. Openings are formed in the insulating layer. For example, the region over the connector 203 is etched away to define a trench 202. Then, a barrier layer 205 is formed over the surface, including the opening 202. Such a barrier layer 205 is typically formed of tantalum (Ta) containing materials, although other barrier materials can be used. After forming the barrier layer 205, a copper seed layer 206 is formed over the barrier layer 205. The seed layer 206 provides a conductive surface for the subsequent deposition of a bulk copper layer 207 (which fills in the trench 202 and covers the rest of the surface). Such bulk copper layers 207 are often formed using electroplating, but other deposition techniques are also possible. The bulk copper layer 207 is then planarized, for example, using chemical mechanical polishing (CMP).
FIGS. 4 and 5 illustrate the formation of a conventional capping layer. Referring to FIG. 4, a layer of barrier material 208 is formed over the surface of the substrate. Commonly, such layers are formed to a thickness on the order of 500 xc3x85. Subsequently, the layer of barrier material 208 is patterned and masked with photoresist 209. Holes can be etched in regions of barrier material 208 to make connections to underlying conducting layers. As shown in FIG. 5, the surface is etched so that a capping layer 210 of barrier material is formed over the opening 202 in the dielectric layer 201. Subsequently, the photoresist layer is removed, leaving the capping layer 210 in place.
Although suitable for their intended purposes, conventional capping layers are relatively thick, require additional alignment and masking steps, and require additional etching to create the final structure. Improvements in such capping layers can be made. The principles of the present invention are directed toward improved capping layers and improved methodologies for constructing capping layers.
In accordance with the principles of the present invention, the invention includes structure and method for forming alloy capping layers over conducting layers in semiconductor structures. One embodiment comprises a structure including a capping layer of alloy material formed over a copper-containing conducting layer, the alloy configured to prevent diffusion of copper through the capping layer. Such an embodiment can include self-aligned capping layers. Specific embodiments include capping layers formed of copper alloys. In particular, copper alloys that include alkaline earth metals including, but not limited to calcium, strontium, barium, and elements from other groups, including but not limited to cadmium or selenium.
One method embodiment includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer.
In another embodiment, a substrate having formed thereon electrically conducting layer comprised of a copper-containing material is provided. A layer of reactive material is then formed on the surface of the substrate. A portion of the layer of reactive material reacts with the copper-containing material of the conducting layer to form an alloy material that is resistant to copper diffusion, the alloy material being formed on the conducting layer. Unalloyed reactive material is removed from the substrate by heating the substrate to a temperature where the unalloyed reactive material desorbs from the surface of the substrate but where the alloy material remains in place on the substrate surface. The resulting structure is a self-aligned capping layer. In another embodiment, the process is repeated iteratively until a capping layer having the desired thickness is formed.
In another method embodiment, a non-self-aligned capping layer is formed on a copper-containing conducting layer. The method includes the operations of forming a layer of reactive material on the surface of the substrate and reacting a portion of the layer of reactive material with the copper-containing material of the conducting layer to form an alloy material on the conducting layer. The layer of reactive material is pattern masked to create a pattern wherein a mask material masks the reactive material over the conducting layer. The layer of reactive material not covered by the mask is etched away and the mask material is then removed. Remaining unreacted material in the remaining reactive layer is removed from the substrate leaving alloy material in place to form the capping layer. In one embodiment, this remaining unreacted material can be removed by heating the substrate to a temperature where the remaining unreacted material desorbs from the surface of the substrate but where the alloy material remains in place on the substrate surface thereby forming the capping layer.
These and other aspects of the invention will be disclosed in greater detail in the following detailed description.